____________________Introduction____________________

These files can be used to demonstrate the USB interface working on a
BurchED B5-X300 board with Xilinx's Web-Pack software. This is a simple
getting started guide.

Connect the USB interface to header F MAKING SURE THE VOLTAGE SELETION
JUMPER FOR HEADER F IS SET TO 5V, and a B5-LEDS module to header D
if you've got one.

Copy the vhdl files into a designated 'project' directory.

____________________Create Project____________________

Run up Web-Pack and select File->New Project

Call the project whatever you want, and select the target project
directory. Check the device family and device are correct 
(Spartan2E, XC2S300E-6pq208) then click on the Design Flow 
box and chande the entry from EDIF to XST VHDL, hit OK.


____________________Add VHDL files to project____________________

Select Project->Add Source. Select usb_if.vhd and chip.vhd and hit
OK. When asked confirm these are both VHDL Modules.

Webpack should then read in both files and detect that chip.vhd is the 
top level design module.


____________________Change Project Constraints____________________

In the "Processes for Current Source" window, expand out the 
Design Entry Utilities then the User Constraints options.

Double click on the Edit Implementation Constraints File and 
the *.ucf file for the project will be opened. Cut and past
the contents of the CHIP.UCF (that was downloaded) into the
*.ucf file then save and close it.

Expand the "Implement Design" option, then right click on "Place
and Route" and select Properties. Click on and change the "Place
and Route Effort Level(Overall)" from Default(Low) to High.
Check that Use Bonded IOs is selected. Hit OK.


____________________Synthesise, Place and Route the design_______________

Double click on "Place & Route" and Webpack will synthesis, place and
route the design. This will take a minute or two.


____________________Generate the Programming file____________________

Right click on "Generate Programming File" and select Properties.
Under the "Startup Options" tab change the "Start-Up Clock" to
JTAG Clock. Hit OK.

Double click on "Generate Programming File" and the programming file
should be created in a few seconds.


____________________Programme the target FPGA____________________

Power up the target board, plug in the configuration cable etc.

Expand the "Generate Programming File" option and double click on
"Configure Device(iMPACT)". The programmer window will open and the
target device should be identified correctly.

Righ click on the graphic of the device, check that Verify _isn't_
selected then hit OK. The device will take approximately 15 seconds
to programme as shown in the status bar, the programmer then reports
if the operation was sucessful.

____________________Finish Off_________________________
7) Plug in a USB cable, connect to your PC then refer to the Software
README.txt for instructions on how to load the USB drivers and test
the target design.


